The present invention relates to an analog to digital converter (ADC), and in particular, though not limited to a switched capacitor ADC, which comprises a calibration circuit for compensating for coupling capacitor errors in the ADC, and the invention also relates to a method for calibrating the ADC.
Switched capacitor ADCs for converting a sampled analog voltage of an input signal to a digital output word are known. Such ADCs comprise a capacitor array, which comprises a plurality of binary weighted capacitors which are selectively chargeable through a switch network under the control of switch bits outputted by a successive approximation register (SAR) in response to the output of a comparator which compares the voltage of the capacitor array with a reference voltage. The switch bits outputted by the SAR progressively switch in and out capacitors of the capacitor array until the voltage on the capacitor array is equal to the reference voltage. The digital word formed by the switch bits outputted by the SAR when the respective voltages on the comparator are equal to each other, within the resolution of the ADC, is determined as being the digital word corresponding to the sampled voltage.
In a single stage binary weighted capacitor array the capacitor corresponding to the least significant bit (LSB) is of unit value, namely, 20 unit of capacitance. The capacitor corresponding to the next LSB is of capacitance 21 units of capacitance, and so on up to the capacitor corresponding to the most significant bit (MSB), which in an n bit ADC is of 2nxe2x88x921 units of capacitance. Typically, each capacitor of the capacitor array is provided by the appropriate number of unit capacitors, each of 20 unit capacitance, for example, the capacitor corresponding to the LSB comprises one capacitor of 20 unit capacitance, and the capacitor corresponding to the MSB comprises 2(nxe2x88x921) capacitors, each of 20 unit capacitance. Accordingly, ADCs with high resolution, for example, resolutions beyond eight bits, require an impracticably large number of unit capacitors. This leads to two problems. Firstly, the total capacitance of the array becomes so large that the voltages of the analog input signal and the reference voltage source are unable to drive the array at a reasonable speed, and secondly, the area of silicon on an integrated circuit (IC) chip required for the capacitors becomes uneconomically large. A reduction in the unit capacitor size, which to some extent would assist in overcoming these problems, in general, leads to the ratio accuracy of the ADC being compromised. To overcome these problems and to facilitate the provision of higher resolution ADCs, series-coupled array ADCs are provided.
In a series-coupled array, the capacitor array is divided into at least two capacitor arrays which are capacitively coupled. One of the capacitor arrays is a most significant array and comprises a capacitor array which represents the MSBs, and the second capacitor array is a least significant array comprising an array of capacitors which represent the LSBs. More than two capacitor arrays may be provided, and each capacitor array is capacitively coupled to the next more significant capacitor array. The value of each coupling capacitor which couples one capacitor array to the next more significant capacitor array depends on the parasitic capacitance in the lesser significant of the two capacitor arrays. Such parasitic capacitance is associated with each portion of the capacitor array, and the ideal value of the coupling capacitor Cc in a two array ADC is:       C    c    =            C      1        ⁡          (                                                  C              2                        ⁡                          (                                                2                  L                                -                1                            )                                +                      C            s2                                                              C              2                        ⁢                          2              L                                -                      C            1                              )      
where C1 is the unit capacitance in the most significant capacitor array C2 is the unit capacitance in the least significant capacitor array Cs2 is the parasitic capacitance associated with the least significant capacitor array and L is the number of capacitors in the least significant capacitor array.
Accordingly, it can be seen from the above equation that the capacitive value of the coupling capacitor for coupling a capacitor array with the next more significant capacitor array is dependent on the parasitic capacitance of the less significant capacitor array. When selecting the capacitance of the coupling capacitor, the capacitance is selected in order to compensate for the parasitic capacitance in the less significant capacitor array of the two capacitor arrays which are coupled by the coupling capacitor. However, due to processing variations in the fabrication of an ADC on silicon in an IC chip, the parasitic capacitance, and indeed the capacitance of the coupling capacitor can vary from chip to chip. Thus, there is a need for a calibration circuit for facilitating adjustment of the effective capacitance of the coupling capacitor between a less significant capacitor array and its next more significant capacitor array, for compensating for silicon and processing variations.
U.S. Pat. No. 5,434,569 of Yung, et al provides such a calibration circuit. Yung discloses a switched capacitor ADC which comprises a two array series-coupled capacitor circuit comprising a most significant capacitor array and a least significant capacitor array. The respective capacitor arrays are capacitively coupled by a coupling capacitor. The calibration circuit comprises an array of binary weighted calibration capacitors which are capacitively coupled to the least significant capacitor array through a small capacitor. A switch network is provided for selectively and alternately switching the calibration capacitors to the most significant capacitor array or to a reference voltage. By switching selected ones of the calibration capacitors to the most significant capacitor array the total capacitance value of the capacitive coupling between the least significant capacitor array and the most significant capacitor array can be increased to a value to compensate for under capacitance of the coupling capacitor, and in turn to compensate for the parasitic capacitance in the least significant capacitor array.
While the provision of the calibration circuit in the ADC of Yung is adequate for compensating for under capacitance of the coupling capacitor, it is unsuitable for correcting for over capacitance of a coupling capacitor.
There is therefore a need for an ADC which comprises a calibration circuit which overcomes the problems of prior art calibration circuits.
The present invention is directed towards providing such an ADC, and the invention is also directed towards providing a method for calibrating an ADC.
According to the invention there is provided an analog to digital converter (ADC) comprising:
a first capacitor circuit from which a digital output word is derived corresponding to a sampled analog voltage from an input signal, the first capacitor circuit comprising at least two capacitor arrays of progressively increasing significance, each capacitor array being capacitively coupled to the next more significant capacitor array,
a second capacitor circuit,
a comparator having a first input coupled to the most significant capacitor array, and a second input coupled to the second capacitor circuit, and
a first calibration circuit comprising an array of first calibrating capacitors, coupled to one of the capacitor arrays of the first capacitor circuit which is less significant than the most significant capacitor array, the first calibrating capacitors being selectively coupleable to the second input of the comparator for compensating for capacitance errors in the capacitive coupling between the capacitor array to which the first calibration circuit is coupled and the next more significant capacitor array.
In one embodiment of the invention the first calibrating capacitors of the first calibration circuit are selectively coupleable to the first input of the comparator for compensating for capacitance errors in the capacitive coupling between the capacitor array to which the first calibration circuit is coupled and the next more significant array.
In another embodiment of the invention the first calibrating capacitors of the first calibration circuit are selectively coupleable to a first voltage reference.
Preferably, each of the first calibrating capacitors of the first calibration circuit are selectively coupleable to one of the second input of the comparator, the first input of the comparator, and the first voltage reference.
In one embodiment of the invention the first calibration circuit is coupled to the second most significant capacitor array of the first capacitor circuit.
In another embodiment of the invention the capacitor array of the first capacitor circuit to which the first calibration circuit is coupled is less significant than the second most significant capacitor array.
Preferably, a first calibrating switch network is provided between the first calibrating capacitors of the first calibration circuit and the second input of the comparator for selectively coupling the first calibrating capacitors to the second input of the comparator.
Advantageously, the first calibrating switch network is provided for selectively coupling the first calibrating capacitors of the first calibration circuit to the first input of the comparator. Preferably, the first calibrating switch network is provided for selectively coupling the first calibrating capacitors of the first calibration circuit to the first voltage reference.
In one embodiment of the invention the first calibrating capacitors of the first calibration circuit are coupled through a first common node to the capacitor array of the first capacitor circuit. Preferably, the first common node to which first calibrating capacitors of the first calibration circuit are coupled is capacitively coupled to the capacitor array of the first calibration capacitor circuit by a first coupling capacitor for attenuating the capacitance value effect of the first calibrating capacitors.
In one embodiment of the invention the first common node to which the first calibrating capacitors are coupled is coupled to a voltage reference by a first co-operating attenuating capacitor for co-operating with the first calibration coupling capacitor for attenuating the capacitance value effect of the first calibrating capacitors.
In another embodiment of the invention the first calibrating capacitors of the first calibration circuit are binary weighted relative to each other.
In another embodiment of the invention the capacitors of the capacitor arrays of the first capacitor circuit are selectively switchable for determining the digital word corresponding to the sampled voltage of the input signal.
Preferably, the second capacitor circuit capacitively couples the second input of the comparator to a main voltage reference.
In a further embodiment of the invention the second capacitor circuit comprises respective capacitor arrays corresponding to the capacitor arrays in the first capacitor circuit, each capacitor array of the second capacitor circuit being capacitively coupled to the next more significant capacitor array, and the most significant capacitor array of the second capacitor circuit being coupled to the second input of the comparator.
Preferably, the capacitor arrays of the second capacitor circuit are coupled to the main voltage reference.
In another embodiment of the invention the ADC is adapted for receiving a differential signal, the capacitors of the capacitor arrays of the respective first and second capacitor circuits being selectively switchable for determining a digital word corresponding to a sampled differential voltage of the differential signal.
In one embodiment of the invention the first calibration circuit compensates for capacitance errors in the capacitive coupling in the second capacitor circuit between the two capacitor arrays in the second capacitor circuit, the less significant of which corresponds to the less significant capacitor array of the first capacitor circuit to which the first calibration circuit is coupled.
In one embodiment of the invention a second calibration circuit is provided comprising an array of second calibrating capacitors coupled to one of the capacitor arrays of the second capacitor circuit which is less significant than the most significant capacitor array of the second capacitor circuit, the second calibrating capacitors being selectively coupleable to the first input of the comparator.
In one embodiment of the invention the second calibrating capacitors of the second calibration circuit are selectively coupleable to the first input of the comparator.
In another embodiment of the invention the second calibrating capacitors of the second calibration circuit are selectively coupleable to a second voltage reference.
Preferably, the second calibrating capacitors of the second calibration circuit are selectively coupleable to one of the first input of the comparator, the second input of the comparator, and the second voltage reference.
In one embodiment of the invention the second calibration circuit is coupled to the second most significant capacitor array of the second capacitor circuit.
In a further embodiment of the invention the capacitor array of the second capacitor circuit to which the second calibration circuit is coupled is less significant than the second most significant capacitor array.
Preferably, a second calibrating switch network is provided between the second calibrating capacitors of the second calibration circuit and the first input of the comparator for selectively coupling the second calibrating capacitors of the second calibration circuit to the first input of the comparator. Advantageously, the second calibrating switch network is provided for selectively coupling the second calibrating capacitors of the second calibration circuit to the second input of the comparator.
Advantageously, the second calibrating switch network is provided for selectively coupling the second calibrating capacitors of the second calibration circuit to the second voltage reference.
In one embodiment of the invention the second calibrating capacitors of the second calibration circuit are coupled through a second common node to the capacitor array of the second capacitor circuit. Preferably, the second common node to which the array of second calibrating capacitors of the second calibration circuit is coupled is capacitively coupled to the capacitor array of the second capacitor circuit by a second calibration coupling capacitor for attenuating the capacitive value of the second calibrating capacitors.
In one embodiment of the invention the second common node to which the second calibrating capacitors are coupled is coupled to a voltage reference by a second co-operating attenuating capacitor for co-operating with the second calibration coupling capacitor for attenuating the capacitance value effect of the second calibrating capacitors.
In another embodiment of the invention the second calibrating capacitors of the second calibration circuit are binary weighted relative to each other.
In another embodiment of the invention a first main switch network is provided for selectively and alternately switching the capacitors of the capacitor arrays of the first capacitor circuit to an upper voltage reference and a lower voltage reference for charging thereof.
In a further embodiment of the invention the first main switch network is provided for selectively switching the capacitors of the capacitor arrays of the first capacitor circuit to the input signal, the voltage of which is to be sampled.
In another embodiment of the invention a first charge control switch is coupled to the first input of the comparator for selectively coupling the first input of the comparator to the main voltage reference during sampling of the voltage of the input signal.
In a further embodiment of the invention a second charge control switch is coupled to the second input of the comparator for selectively coupling the second input of the comparator to the main voltage reference during sampling of the voltage of the input signal.
In a still further embodiment of the invention a second main switch network is provided for selectively and alternately switching the capacitors of the capacitor arrays of the second capacitor circuit to the upper voltage reference and the lower voltage reference for configuring the ADC as a differential ADC.
In one embodiment of the invention the second main switch network is provided for selectively switching the capacitors of the capacitor arrays of the second capacitor circuit to one end of a differential input signal, the voltage of which is to be sampled, the capacitors of the capacitor arrays of the first capacitor circuit being selectively switched to the other end of the differential input signal by the first main switch network.
In an alternative embodiment of the invention a first input charge capacitor is connected to the first input of the comparator, and the first input charge capacitor is selectively switchable to the input signal, the voltage of which is to be sampled for charging the first input charge capacitor, and the main voltage reference when the first input charge capacitor has been charged.
In a further alternative embodiment of the invention a second input charge capacitor is connected to the second input of the comparator, and the second input charge capacitor is selectively switchable to one end of a differential input signal, the voltage of which is to be sampled for charging the second input charge capacitor, and the first input charge capacitor when the first and second input charge capacitors have been charged, the first input charge capacitor being selectively switchable to the other end of the differential input signal.
Additionally, the invention provides an analog to digital converter (ADC) comprising:
a first capacitor circuit from which a digital output word is derived corresponding to a sampled analog voltage from an input signal, the first capacitor circuit comprising at least three capacitor arrays of progressively increasing significance, each capacitor array being capacitively coupled to the next more significant capacitor array,
a comparator having a first input coupled to the most significant capacitor array, and a second input coupled to a voltage reference, and
a first calibration circuit comprising an array of first calibrating capacitors, coupled to one of the capacitor arrays of the first capacitor circuit which is less significant than the second most significant capacitor array, the first calibrating capacitors being selectively coupleable to the first input of the comparator for compensating for capacitance errors in the capacitive coupling between the capacitor array to which the first calibration circuit is coupled and the next more significant capacitor array.
In one embodiment of the invention the first calibrating capacitors of the first calibration circuit are selectively coupleable to a voltage reference which may be the same or different to the voltage reference to which the second input of the comparator is coupled.
The invention also provides a method for compensating for capacitance errors in capacitive coupling in an ADC of the type comprising a first capacitor circuit from which a digital output word is derived corresponding to a sampled analog voltage from an input signal, the first capacitor circuit comprising at least two capacitor arrays of progressively increasing significance, each capacitor array being capacitively coupled to the next more significant capacitor array, and a comparator having a first input coupled to the most significant capacitor array and a second input coupled to a second capacitor circuit, the method comprising the steps of coupling a first calibration circuit comprising an array of first calibrating capacitors to one of the capacitor arrays of the first capacitor circuit which is less significant than the most significant capacitor array, and selectively coupling the first calibrating capacitors to the second input of the comparator for compensating for the capacitance errors in the capacitive coupling between the capacitor array to which the first calibration circuit is connected and the next more significant capacitor array until the capacitance errors in the capacitive coupling have been compensated for.
In one embodiment of the invention the first calibrating capacitors of the first calibration circuit which are not coupled to the second input of the comparator are coupled to a first voltage reference.
In another embodiment of the invention the first calibrating capacitors are selectively coupled to one of the second input of the comparator and the first input of the comparator for compensating for capacitance errors in the capacitive coupling between the capacitor array to which the first calibration circuit is coupled and the next more significant capacitor array until the capacitance errors in the capacitive coupling have been compensated for, and the first calibrating capacitors which are not coupled to one of the first input and the second input of the comparator are coupled to the first voltage reference.
The advantages of the invention are many. The ADC according to the invention can be readily easily calibrated with a relatively high degree of accuracy. The provision of the first calibration circuit permits accurate compensation for any errors in the value of the capacitive coupling between the capacitor array to which the first calibration circuit is coupled and the next more significant capacitor array, and where the capacitive coupling also takes into account the effect of parasitic or unswitched capacitance in the less significant capacitor array, the parasitic capacitance is also compensated for. When the first calibration circuit is provided with the first calibrating capacitors selectively switchable to the second input of the comparator, over capacitance of the capacitive coupling between the capacitor array to which the first calibration circuit is coupled and the next more significant capacitor array is compensated for. When the first calibrating capacitors of the first calibration circuit are selectively switchable to the first input of the comparator, under capacitance in the capacitive coupling is compensated for. However, a particularly important advantage of the invention is achieved when the first calibrating capacitors of the first calibration circuit are selectively coupleable to one or other of the first and second inputs of the comparator, since both under and over capacitance in the capacitive coupling is compensated for. In other words, bi-directional compensation for capacitance errors in the capacitive coupling is provided for.
Additionally, by providing the first calibrating capacitors to be selectively switchable to one or other of the first and second inputs of the comparator, and also to the first voltage reference has the particularly important advantage that it effectively doubles the calibration range, while maintaining the calibration resolution. By providing the first calibration circuit with the first calibrating capacitors selectively switchable to the second input of the comparator and the first reference voltage permits those of the first calibrating capacitors not to required for calibration to be switched to the first reference voltage.
A further and particularly important advantage of the invention is achieved when the first calibrating capacitors of the first calibration circuit are selectively switchable to one or other of the first and second inputs of the comparator, thereby facilitating compensating for both under and over capacitance of the coupling capacitor between the capacitor array to which the first calibration circuit is coupled and the next more significant capacitor array. When the unit capacitance value of the capacitors of the two arrays are equal, the coupling capacitor can also be made equal to the unit capacitance value of the capacitors of the two capacitor arrays. Since a unit size coupling capacitor provides better matching to the rest of the capacitor arrays, a smaller calibration range is required from the first calibration circuit.
The provision of the first calibration circuit and its arrangement in the ADC is particularly suitable for both single ended and differential switched capacitor ADCs of balanced architecture, although the first calibration circuit and its arrangement in the ADC according to the invention is also suitable for single ended switched capacitor ADCs of non-balanced architecture, where the two inputs of the comparator are not capacitively balanced. Furthermore, the ADC may be provided as a single ended switched capacitor circuit of non-balanced architecture of the type where the first input of the comparator is coupled to the most significant capacitor array, and the second input of the comparator is coupled directly to a reference voltage, for example, to ground. In the case of such a single ended non-balanced switched capacitor ADC, the first calibration circuit is arranged so that the first calibrating capacitors are selectively switchable to the first input of the comparator, and preferably, the first calibration circuit is arranged so that the first calibrating capacitors are selectively switchable to one or other of the first input of the comparator and the first voltage reference. In this case the calibration circuit is particularly suitable for calibrating capacitive coupling between the second most significant capacitor array and its next less significant capacitor array.
The ADC according to the invention with the first calibration circuit is also ideally suited for adaptation as a differential ADC, and when provided as a differential switched capacitor ADC, a single first calibration circuit is sufficient for compensating for capacitive coupling in both the first and second capacitor circuits. However, where a second calibration circuit is provided coupled to a capacitor array of the second capacitor circuit, as well as a first calibration circuit coupled to a corresponding capacitor array of the first calibration circuit, the calibration range is increased and the first and second inputs to the comparator are better balanced for increasing rejection of noise interference from other parts of the ADC circuitry. The advantages obtained by providing the various switching arrangements for switching the second calibrating capacitors to one or other of the first input to the comparator and the first voltage reference on the one hand, and to one or other of the second input of the comparator and the first voltage reference on the other hand are similar to those already described with reference to the first calibration circuit. The advantage of providing the second calibrating capacitors to be selectively switchable to one of either the first and second inputs of the comparator and the first voltage reference are also similar to those described with reference to the first calibration circuit.
A further advantage of the invention is achieved by virtue of the fact that the calibration switches of the calibration network in each calibration circuit are located so that they are between the calibrating capacitors and the one of the first and second inputs of the comparator and ground, and thus the switches of the calibration network are never coupled to a capacitor array which is less significant than the most significant capacitor array. The advantage of this is that the inherent capacitance of the switches of the calibration switch network has little or no effect on the most significant capacitor array, in other words, the inherent capacitance of the switches of the calibration switch network cause little or no matching errors in the most significant capacitor array, due to the fact that the voltage on the first or second input to the comparator is substantially the same at the end of a conversion as it is directly after the input signal has been sampled. Whereas if the switches of the calibration switch network were to have been connected to a capacitor array of less significance than the most significant capacitor array, the inherent capacitance of the switches coupled to the less significant capacitor array would cause unwanted matching errors. This is a particularly important advantage which is achieved by the present invention which overcomes one of the problems of the ADC of Yung in U.S. Pat. No. 5,434,569, since if Yung were to use his calibration circuit for compensating for capacitance errors in a coupling capacitor coupling to capacitor arrays wherein the more significant capacitor array was the second most significant capacitor array or a lesser significant capacitor array, the switches of the switch network of Yung would have to be coupled to one or other of the capacitor arrays which would be less significant than the most significant capacitor array.